Display device and method of producing same

ABSTRACT

A driver circuit-integrated type active matrix substrate  212  has, on a glass substrate  210 , a liquid crystal display unit  221  including a matrix array composed of thin film transistors, and driver circuits  224–226  for driving the liquid crystal display unit. A peripheral portion of the glass substrate  210  has recessed grooves  260–263  formed therein, and power supply lines  251–254  for supplying power to the driver circuits  225  and  226  are buried in the recessed grooves. Such a configuration reduces the resistance of bus wiring lines such as the power supply lines for the driver circuits and data lines, without increasing an area of the peripheral portion. The driver circuit-integrated type active matrix substrate reduces an amount of voltage drop in power supply voltage, ensuring reliable operation of the driver circuits.

TECHNICAL FIELD

The present invention relates to a display device and a method ofproducing the device, more particularly to a structure of the connectionbetween an integrated driver circuit section formed on an arraysubstrate and bus lines such as a power supply line for supplyingelectric power to the integrated driver circuit section or a data linefor supplying data thereto.

BACKGROUND ART

Background Art—I

In a conventional active matrix type liquid crystal display deviceemploying amorphous silicon (hereafter referred to as “a-Si”)transistors, a-Si has been considered sufficient to meet the performancerequirements for driving the pixels. However, using a-Si, integrating asignal driver circuit on the very substrate on which the pixels areformed is difficult because of the characteristics of a-Si. For thisreason, the display panel is usually driven by an external drivercircuit (also simply referred to as a driver) formed by using singlecrystal Si.

In such a device, it is necessary to connect IC chips in the driver tothe array substrate. An example of a technique for the connecting is thetape carrier package (TCP), as shown in FIG. 31, in which a driver 302is mounted on a tape carrier film 301 so as to be connected to an arraysubstrate 303 of the liquid crystal display panel.

In order to achieve a reduction in the thickness and weight of thedevice, the chip on glass (COG) technique, in which a driver is directlymounted on a liquid crystal panel, has been suggested. This techniqueeliminates the tape carriers and accordingly achieves cost reduction. Inaddition, the total number of the connections in a liquid crystal panel,including the connections with drivers, is reduced to ⅓ to ⅕ of that inTCP, resulting in an increase in reliability. This technique isillustrated in FIG. 32.

Although the number of connections of the driver IC chips is smaller inCOG than that in TCP, COG also requires a high precision mountingprocess to connect a large number of terminals, which makes it difficultto achieve a significant increase in reliability and a remarkablereduction in manufacturing costs.

Unlike liquid crystal display devices using amorphous silicon TFTs forthe switching elements of the active matrix, liquid crystal displaydevices employing polysilicon TFTs (hereafter referred to as p-Si TFTs)exhibit a mobility of the semiconductor layer at least 10 times to 100times higher than that of a-Si (see SID 97, p. 171) and therefore makeit possible to integrally form both active matrix elements for thedisplay and portions of or all of signal driver circuits on a glasssubstrate at one time.

The driver circuit comprises, for example, shift registers, latches, andso forth, formed by a multiplicity of CMOS (Complimentary Metal OxideSemiconductor) inverters, each composed of a p-channel TFT 304 and ann-channel TFT 305 as shown in FIG. 33. The wiring lines connecting thep-channel TFTs 304, the power supply lines, and the image signal linesare composed of, for example, an aluminum thin film that is formed onthe glass substrate and has a thickness of about 7000 Å.

In the prior art liquid crystal display device, owing to thecharacteristics of p-Si TFT and line resistance of the power supplyline, a voltage drop occurs in the power supply voltage, which issupplied to the shift resisters and so forth. Therefore, the prior artliquid crystal display device has such a drawback that unless the widthof the power supply line is made fairly large or the power sourcevoltage is made fairly high, the driver circuit does not properlyoperate.

As mentioned above, p-Si TFTs can achieve a higher operation speed thana-Si TFTs. However, as shown in, for example, “Integrated drivercircuits for active matrix liquid crystal displays,” Displays Vol. 14,No. 2, 1993, pp. 104–114 (see FIGS. 34( a) and 34(b)), p-Si TFTs have alarger OFF current and a larger subthreshold region current than thosein single crystal silicon transistors, which are generally used in ICchips. This is considered to be due to the hopping of carriers betweengrain boundary levels in polysilicon or due to the influence of fixedcharge caused by ions present in the gate insulating layer (MemorandumNo. UCB/ERL M93/82). For this reason, in a switching operation of theCMOS inverter, as a drain current increases in the subthreshold region,a larger shoot-through current occurs.

Referring now to FIG. 35, more specific details of the shoot-throughcurrent are illustrated below.

(1) When an input voltage (gate voltage) V_(in) is 0 V, the p-channelTFT 304 is in an ON state and the n-channel TFT 305 is in an OFF state,and the output voltage V_(out) becomes a high level (5V=V_(dd)). In thisstate, substantially no shoot-through current (DC path current) flowsfrom the source of the p-channel TFT 304 to the drain of the n-channelTFT 305.

(2) During the period in which the input voltage V_(in) increases andexceeds a threshold voltage V_(th(n)) (voltage A) of the n-channel TFT305 and reaches a voltage B, the p-channel TFT 304 maintains the ONstate in a saturation region, while the n-channel TFT 305 is in anon-saturation region and a drain current corresponding to the inputvoltage V_(in) starts to flow. Accordingly, the shoot-through currentgradually increases, while the output voltage V_(out) graduallydecreases.

(3) During the period in which the input voltage V_(in) furtherincreases from the voltage B and reaches a voltage D, both p-channel TFT304 and n-channel TFT 305 are in a non-saturation region and a draincurrent corresponding to the input voltage Vin flows therein.Accordingly, the shoot-through current reaches the maximum value at avoltage C, and the output voltage V_(out) shows a sudden drop.

(4) When the input voltage Vin exceeds a voltage D, the p-channel TFT304 is in a non-saturation region and a drain current corresponding tothe input voltage Vin flows therein, while the n-channel TFT 5 is in anon-saturation region and substantially in a ON state. Accordingly, theshoot-through current reduces, and the output voltage V_(out)asymptotically approaches a low level (0 V).

(5) When the input voltage V_(in) exceeds the threshold voltageV_(th(p)) (voltage E), the p-channel TFT 304 is turned to an OFF stateand the n-channel TFT 305 an ON state. Accordingly, the output voltageV_(out) becomes the low level (0 V) and substantially no shoot-throughcurrent flows therein.

Since such a shoot-through current occurs as described above, when theamount of the voltage drop caused by the line resistance of the powersupply lines becomes 1.5 V or greater, margins of driving voltage forshift registers and latches become exceedingly small, making the drivercircuits difficult to properly operate. Specifically, when a liquidcrystal display device being 20 cm in diagonal size is required, acurrent of about 160 mA flows in a power supply line thereof In such adevice, in order to control the voltage drop within 1.5 V or smaller, itis required that the wiring line resistance of the power supply line beabout 9 Ω or lower. Therefore, when the sheet resistance of the powersupply line is 0.1 Ω, the width of the wiring line needs to be 3.4 mm orlarger per line, in order to ensure proper operation of the drivercircuits.

Such a problem is more serious in the cases of liquid crystal displaydevices having a large number of display pixels and liquid crystaldisplay devices capable of color display, since in these devices, thenumber of stages of shift registers is large and the voltage drop in thepower supply voltage is accordingly large. Furthermore, although such aproblem also arises both in liquid crystal display devices operated byanalog image input signals and in those operated by digital image inputsignals, but especially the latter devices are more susceptible to theproblem since they have, in addition to the shift registers, latchcircuits and D-A converters corresponding to the bit number of thedigital image signals and the shoot-through current is correspondinglylarge.

The above-described problem also exists in a so-called point-at-a-timedriving type liquid crystal display device, in which image signalvoltage is sequentially applied to the pixel electrodes, such as shownin Japanese Examined Patent Publication No. 4-3552, and in aline-at-a-time driving type liquid crystal display device, in whichimage signals for one horizontal period is retained and thereafter imagesignal voltages are applied to the pixel electrodes of the horizontalline at one time, such as shown in SID '96 Digest pp. 21–24.

Background Art-II

At present, liquid crystal display devices are widely used in suchappliances as notebook computers and automobile navigation systems, andin the devices, further reduction in size and thickness is desired. Inorder to achieve the size and thickness reduction, the use ofpolycrystalline silicon thin film transistors, which makes it possibleto integrate driver circuits in the array substrate, is consideredeffective to simplify the manner of connection of the driver circuitswith external circuits.

Accordingly, in the following discussion referring to drawings, thereare described a prior art device in which amorphous silicon thin filmtransistors are connected to driver ICs for driving the transistors byusing flip chip technique and a prior-art connection technique forconnecting a prior art device in which polycrystalline silicon thin filmtransistors are used to external circuits.

FIGS. 36 and 37 schematically show the configurations of a 5-inch liquidcrystal display device having about 400 thousand pixels. FIG. 36 shows aplan view of a liquid crystal display device in which prior artamorphous silicon thin film transistors are connected to driver ICs byusing a flip chip technique, and a cross-sectional view of the devicetaken along the line A–A′ in the plan view. FIGS. 37(A) and 37(B) show aplan view of a liquid crystal display device in which the driver circuitis made of a polycrystalline silicon thin film and a cross-sectionalview of the device taken along the line B–B″.

In FIGS. 36(A), 36(B), 37(A), and 37(B), like parts are designated bylike reference numerals. Reference numeral 401 indicates an arraysubstrate, reference numeral 402 a counter substrate, reference numeral402 a flexible wiring board, and reference numeral 411 a driver IC.

As shown in FIGS. 36(A) and 36(B), in a device in which ICs areconnected using a flip chip technique, if an additional flexible wiringboard were not provided, the pitches of the connections would be sosmall that they would be beyond the current state of the art, andtherefore, flexible wiring boards are provided on opposing sides and areconnected to a printed circuit board (not shown) to construct circuitry.

The device shown in FIGS. 37(A) and 37(B) has a driver circuit sectionformed of a polycrystalline silicon thin film. Unlike the prior artamorphous silicon thin film transistors, the signal circuit section canbe formed on one side, and therefore only one flexible wiring board isrequired for the connection with the printed wiring board to constructthe circuitry.

As described above, the prior art method in which amorphous silicon thinfilm transistors and driver ICs are connected using a flip chiptechnique requires two flexible wiring boards, which increases devicecosts, and moreover, since the device has such a configuration that bothsides of the flexible wiring boards are connected by a printed wiringboard disposed on the side of the backlight, the liquid crystal devicebecomes bulkier.

When the driver circuits are formed using polysilicon thin filmtransistors, the flexible wiring board is necessary only for one sidebecause there are no restrictions in the connection pitches andaccordingly cost reduction is possible to a certain degree. However, theflexible wiring board must be connected to a relatively large shapedprinted circuit board, which requires that the printed wiring board bedisposed on the backside of the device, and the problem that the liquidcrystal device is bulky remains unsolved.

SUMMARY OF THE PROBLEMS IN THE PRIOR ART

In summary, in order to ensure proper operation of the driver circuits,there is a need for low resistance bus lines for supplying power and forsupplying various other signals. In addition, there is a need forreduction in the size and thickness of a flexible wiring board forconnecting the device with external circuits, thereby reducing the sizeand thickness of the display device.

DISCLOSURE OF THE INVENTION

In view of the foregoing and other problems in the prior art, it is anobject of the present invention to provide a display device having a lowresistance bus line formed therein, which can achieve a device sizereduction and a device thickness reduction by reducing the size of aflexible wiring board for connecting the device to an external circuit.It is another object of the invention to provide a method of producingsuch a device.

In order to accomplish the foregoing and other objects of the invention,a resin substrate having a bus line is mounted on an active matrixsubstrate in one embodiment of the invention. In another embodiment, thebus line is formed on an active matrix substrate by printing. In furtheranother embodiment, the bus line is buried in an active matrixsubstrate.

(1) Specific configurations of Embodiment 1 according to the inventionare as follows.

In Embodiment 1 of the present invention, there is provided a displaydevice comprising an active matrix substrate having a driver circuitsection composed of a plurality of polycrystalline silicon thin filmtransistors, a counter substrate, a liquid crystal filled between theactive matrix substrate and the counter substrate, and anindividually-wired line array for supplying a clock signal, a datasignal or electric power to a plurality of circuit elements comprised inthe driver circuit section, wherein the individually-wired line array isextended to a peripheral portion of the active matrix substrate, thedisplay device characterized in that: the peripheral portion of theactive matrix substrate has an insulator having a via hole and amulti-layer bus line-equipped section having a bus line formed on theinsulator, the bus line is connected to the individually-wired linearray via the via hole, and the bus line has a connecting terminal forconnecting the display device to an external circuit.

The above-described configuration makes it possible to form a lowresistance bus line in a peripheral portion of the active matrixsubstrate. In addition, a connecting terminal to an external circuit isprovided at a part of the bus line to reduce the size and thickness ofthe flexible wiring board.

For the multi-layer bus line equipped section, a pre-formed resinsubstrate may be used. The resin substrate has, of course, a bus lineformed on the surface thereof, and a via hole formed in the interiorthereof. For the material for the resin substrate, aramid-epoxy resin ispreferable. As a conductive member in the via hole, a conductive pastemay be used.

The resin substrate may have a multi-layer structure having a pluralityof layers in which a bus line is provided on a surface of an inner layerthereof as well as on a surface of the uppermost layer thereof, and thebus lines are selectively connected to each other via a via hole formedin each of the layers to form a three-dimensional wiring structure. Sucha multi-layer substrate allows more freedom in designing the bus line 12to easily arrange a plurality of bus lines 12.

In addition, the electrically conductive paste may partially protrudefrom a lower opening of the via hole, and the active matrix substrateand the resin substrate may be bonded together with the protrudingportion of the electrically conductive paste. Thereby, a bump terminaland a conductive adhesive may be eliminated.

In addition, the resin substrate and the active matrix substrate may bebonded with an adhesive composed of a material having thermoplasticproperty. Accordingly, when the resin substrate is secured to the activematrix substrate, the attachment and detachment can be carried out manytimes, ensuring an accurate alignment of the resin substrate and theactive matrix substrate.

In addition, the adhesive may be an anisotropic conductive resin or asilver paste.

In addition, the resin substrate may be a film substrate and may bedetachably bonded to the active matrix substrate. The film substrate hasflexibility, which makes it easy to carry out the bonding work.Therefore, the alignment of the resin substrate and the active matrixsubstrate is made more accurate. It is preferable that the filmsubstrate be made of a resin comprising polyimide or epoxy.

In addition, a semiconductor chip comprised in the external circuit maybe mounted on the resin substrate and be connected to the bus line. Thisconfiguration eliminates the need for a flexible wiring board or aprinted wiring board on which an external circuit is mounted.

In addition, the semiconductor chip may be buried in the via hole.Thereby, the surface of the resin substrate is planarized.

(2) Specific configurations of Embodiment 2 according to the presentinvention are as follows.

The multi-layer bus line-equipped section employs a bus line formed byprinting, in place of the resin substrate. The insulator in themulti-layer bus line-equipped section is also formed by printing. Such amulti-layer bus line-equipped section formed by printing also achieves acost reduction in the flexible wiring board and a device size reduction,as well as the case of using a resin substrate. Furthermore, printinghas such an advantage that a low resistance conductive material can beformed only in a required region.

Specific methods of a liquid crystal display device according toEmbodiment 2 are as follows.

In Embodiment 2, there is provided a method of producing a liquidcrystal display device, comprising: forming a driver circuit sectionusing a polycrystalline silicon thin film transistor; forming aninsulating film on a thin film wiring region including the drivercircuit section; forming a via hole by etching a prescribed portion ofthe insulating film by photolithography so that a prescribed portion ofa wiring electrode of the driver circuit section is exposed; printing aprescribed pattern on the insulating film with an electricallyconductive ink; and electrically connecting the pattern to the wiringelectrode of the driver circuit section via the via hole.

In the above-described method, as the insulating film, a silicon nitridefilm or a silicon oxide film provided for protecting pixel sections andthe driver circuit section is utilized, and therefore, it is notnecessary to form an additional insulating film. In addition, by usingan insulating film having good heat resistance, a curing temperature ofthe material to be printed can be made high, and therefore, furtherreduction in the resistance is achieved.

In Embodiment 2, there is also provided a method of producing a liquidcrystal display device, comprising: forming a driver circuit sectionusing a polycrystalline silicon thin film transistor; printing aninsulating film for forming a via hole in a prescribed position in athin film wiring region including the driver circuit section such that aportion of the thin film wiring electrode is exposed; printing aprescribed pattern using an electrically conductive ink; andelectrically connecting the pattern with the wiring electrode of thedriver circuit section via the via hole.

By employing the above-described method, in addition to the insulatingfilm for protecting transistors in pixel sections and driver circuitsections, an insulating film having a low dielectric constant isprovided, and thereby, adverse effects caused by a large current areprevented and a high performance liquid crystal display device isachieved.

In Embodiment 2, there is also provided a method of producing a liquidcrystal display device, comprising: forming a driver circuit sectionusing a polycrystalline silicon thin film transistor; forming aplanarizing film over a pixel region and a thin film wiring line regionincluding the driver circuit section by applying a transparentinsulating film; providing a via hole at a plurality of a prescribedposition in the thin film wiring line region and the pixel region by aphotolithography and an etching process; patterning a transparentconductive film on a prescribed position of the planarizing film; andprinting a wiring line for supplying electric power to the drivercircuit over the planarizing film including the transparent conductivefilm.

In the above-described method, a planarizing film provided for thepurpose of increasing an aperture ratio of the liquid crystal displaydevice is also formed on the driver circuit section so as to be utilizedas an insulating film, and at the same time, a transparent conductivefilm is formed for the electrical connection with the wiring electrodesof the driver circuit section, so that sufficient electrical conductioncan be obtained even when the via holes have a very small size. Thus,the above-described method achieves a further device size reduction.

(3) Specific configurations of Embodiment 3 are as follows.

i) In Embodiment 3, there is provided a display device comprising anactive matrix substrate having a driver circuit section composed of aplurality of polycrystalline silicon thin film transistors, a countersubstrate, a liquid crystal filled between the active matrix substrateand the counter substrate, and an individually-wired line array forsupplying a clock signal, a data signal or electric power to a pluralityof circuit elements comprised in the driver circuit section, wherein theindividually-wired line array is extended to a peripheral portion of theactive matrix substrate, the display device characterized in that: theactive matrix substrate has a recessed groove formed in the peripheralportion; and a bus line to be connected to the individually-wired linearray is buried in the groove.

In this configuration, when a thickness of the bus line is increased byincreasing a depth of the recessed groove, the wiring line resistancecan be reduced and the voltage drop of the power supply voltage can beminimized. As s result, reliable operation of the driver circuit isachieved.

Moreover, wiring line resistance can be reduced without increasing anarea of the peripheral portion of the active matrix substrate, whichmakes it possible to realize a liquid crystal display device having anarrow frame.

Furthermore, since the bus line is buried in the active matrixsubstrate, surface level irregularities are not caused on the connectinglines that connect the bus line to driver circuits and on the insulatingfilm provided over the connecting lines, achieving the planarization ofthe substrate surface. Accordingly, it is made possible to produce aliquid crystal display device having a uniform cell gap.

For a method of burying bus lines in an active matrix substrate, it ispossible to select options such as the following methods: a method inwhich a resist is applied on an active matrix substrate, physicaletching of the active matrix substrate is carried out by sandblasting soas to form recesses, and thereafter the resist is removed to form metalwiring lines; or a method in which a glass is chemically etched using anetchant solution to provide recesses. Physical etching, such as asandblasting method and the like, does not require complex productionapparatuses and manufacturing cost is low, but it is inferior to amethod using an etchant solution in terms of producing wiring lines witha very small width. In contrast, chemical etching using an etchantsolution necessitates an expensive production apparatus and thus a largemanufacturing cost but is superior to a sandblasting method in terms ofthe precision in the etching.

ii) In Embodiment 3, the active matrix substrate may have an organicresin layer in the peripheral portion thereof, and a bus line to beconnected to the individually-wired line array may be buried in theorganic resin layer.

By employing such a configuration, because of the buried wiringstructure, the wiring line resistance can be reduced without increasingthe area of the peripheral portion of the active matrix substrate, thusachieving a liquid crystal display device having a narrow frame as inthe embodiments mentioned above.

In addition, the resin layer serves as a planarizing layer, thusachieving a liquid crystal display device having a uniform cell gap, asin the embodiments mentioned above.

In addition, when a photosensitive material is used for the resinmaterial, the need for coating a resist is eliminated, and theprocessability is improved in comparison to a glass substrate. Inaddition, the organic resin may be coated only on a required region,such as on the peripheral region, by using a screen. In addition, asmetal wiring lines to be buried in the resin, a conductive thermosettingresin may be used and the wiring lines may be printed using a screen.

iii) In addition to the above two configurations, the wiring line to beburied may be a metal fine wire, in place of a thin film or a thickfilm.

iv) In addition, in order to further reduce the resistance of the busline, plating may be employed as a means for increaseing the filmthickness. Suitable materials for the plating may include copperplating, nickel plating, chromium plating, and aluminum plating, whichare effective to reduce the resistance. A plating of alloys thereof mayalso be employed. Further, when the bus line produced by plating forms alayered structure comprising a copper foil layer, a copper platinglayer, and a gold-nickel plating layer, the formation of stable wiringlines is possible.

v) By employing a buried wiring structure, the resistance value of thebus lines is remarkably reduced. The reason is discussed below. Forexample, in a liquid crystal panel being 20 cm in diagonal size, acurrent flowing in a power supply line to shift registers in the drivercircuit utilizing polysilicon is about 800 mA. Accordingly, if the powersupply line is made of Al, which is generally used as a low resistancewiring material in production processes of liquid crystal panels, inorder to control the voltage drop of the power supply line within 1.5 Vor lower, it is necessary that the wiring resistance be 1.8 Ω or lower.Assuming the sheet resistance of Al 0.1 Ω/□, the total width of thewiring lines including both plus and minus lines should be about 13 mm.However, if a plating process is employed, for example, it is easy toproduce a wiring line having a film thickness of 1–10 μm, and forexample, when the film thickness of Al is made 4 μm, the sheetresistance can be reduced to 0.01 Ω/□. If the wiring line width is about4–5 mm, the wiring line resistance is about 0.1 Ω and the voltage dropcaused thereby is hardly a problem. Here, an example in which the buriedwiring lines are formed by a plating process is discussed, but the samediscussion also applies to other variations of the present invention,such as the ones with metal fine wires. For example, in the case ofmetal fine wires, if the diameter is 1–10 μm, the resulting wiring lineresistance is about 0.1 Ω and the same effect as that in the case of theplating process can be obtained.

Of course, the buried wiring structure can be employed for common wiringlines other than power supply lines, such as data lines, clock lines ofshift registers, and the like, which lines have signal delays caused bywiring line resistance, and thereby similar advantageous effects in thecase of the power supply line are achieved.

It is noted that the display devices according to Embodiments 1–2 arenot limited to liquid crystal display devices, but are similarlyapplicable to a display device having a light emission type matrixpanel, such as plasma discharge panels (PDP) and electro-luminescent(EL) displays.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a display panel of Example 1-1.

FIG. 2 is a schematic view showing the state of wiring in the peripheralportion of the display panel.

FIG. 3 is a cross-sectional view of a peripheral portion of the displaypanel.

FIG. 4 is a cross-sectional view showing a display panel of Example 1-2.

FIG. 5 is a cross-sectional view showing a display panel of Example 1-3.

FIG. 6 is a cross-sectional view showing a display panel of Example 1-4.

FIG. 7 is a cross-sectional view showing a display panel of Example 1-5.

FIGS. 8(A) and 8(B) illustrate the principle of Embodiment 2, in whichFIG. 8(A) shows a plan view of a liquid crystal display device accordingto Embodiment 2 and FIG. 8(B) shows a cross sectional view of the liquidcrystal display device.

FIG. 9 is an enlarged cross-sectional view of FIG. 8(B).

FIGS. 10(A) to 10(C) are cross-sectional views illustrating the majorsteps in the process of producing a liquid crystal display device ofExample 2-1.

FIGS. 11(A) to 11(C) are cross-sectional views illustrating the majorsteps in the process of producing a liquid crystal display device ofExample 2-2.

FIGS. 12(A) to 12(C) are cross-sectional views illustrating the majorsteps in the process of producing a liquid crystal display device ofExample 2-3.

FIG. 13 is a plan view showing a liquid crystal display device ofExample 3-1.

FIG. 14 is a circuit diagram of a liquid crystal display device ofExample 3-1.

FIG. 15 is a circuit diagram showing the configurations of shiftregisters 234 to 237 shown in FIG. 14.

FIG. 16 is a timing chart showing the operation of shift registers 234to 237.

FIG. 17 is a graph showing the relationship between the number of thestages of shift registers and the writing time of image signal voltage.

FIG. 18 is a schematic plan view of an array substrate 212.

FIG. 19 is a cross-sectional view taken along the line X1—X1 in FIG. 18.

FIG. 20 is a cross-sectional view taken along the line X2—X2 in FIG. 18.

FIG. 21 is a cross-sectional view taken along the line X3—X3 in FIG. 18.

FIG. 22 shows a variation of the connecting configuration between metalwiring lines and a driver circuit section.

FIGS. 23(1) to 23(5) show a production process of an array substrate ofExample 3-1.

FIGS. 24(1) to 24(6) show a production process of an array substrate ofExample 3-2.

FIG. 25 is a schematic cross-sectional view of an array substrate ofExample 3-3.

FIGS. 26(1) to 26(4) show a production process of an array substrate ofExample 3-3.

FIGS. 27(1) to 27(3) show a production process of an array substrate ofExample 3-4.

FIGS. 28(1) to 28(4) show a production process of an array substrate ofExample 3-5.

FIG. 29 shows a variation of the connecting configuration between metalfine wires and a driver circuit.

FIGS. 30(1) to 30(3) show a production process of an array substrate ofExample 3-6.

FIG. 31 is a plan view showing the configuration of a prior-art liquidcrystal display device made using a tape carrier package.

FIG. 32 is a plan view showing the configuration of a prior-art liquidcrystal display device produced using a chip on glass technique.

FIG. 33 is a circuit diagram showing the configuration of a CMOSinverter.

FIGS. 34( a) and 34(b) are graphs showing the characteristics ofpolycrystalline silicon thin film transistors and single crystal silicontransistors.

FIG. 35 is a graph showing magnitudes of shoot-through currents in aCMOS inverter using polycrystalline silicon thin film transistors.

FIGS. 36(A) and 36(B) are a plan view and a side view of a prior artliquid crystal display device in which an amorphous silicon thin filmand driver ICs are connected using a flip chip technique.

FIGS. 37(A) and 37(B) are a plan view and a side view of a prior artliquid crystal display device with polycrystalline silicon thin filmtransistors.

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1

In Embodiment 1, a resin substrate having a bus line is mounted in aperipheral portion of an active matrix substrate (hereafter alsoreferred to as “an array substrate”), and the bus line is electricallyconnected to a driver circuit section via a via hole formed in the resinsubstrate. This construction makes it possible to form a low resistancebus line in the peripheral portion of the array substrate. In addition,a connecting terminal is provided at a part of the bus line, and therebya reduction in the size and thickness of a flexible wiring board isachieved. Now, Embodiment 1 according to the present invention isspecifically described below by means of Examples 1-1 to 1-5.

EXAMPLE 1-1

FIG. 1 shows a plan view of a display panel made according to Example1-1, FIG. 2 shows the state of the wiring in the vicinity of aperipheral portion of the display panel, and FIG. 3 shows across-sectional view of the vicinity of the peripheral portion of thedisplay panel. A display panel 1 is an active matrix liquid crystaldisplay panel and has an array substrate 2 and a counter substrate 3.Between the array substrate 2 and the counter substrate 3, a liquidcrystal is filled. The array substrate 2 is a driver circuit-integratedtype active matrix substrate in which a driver circuit section 4 (ascanning line driver circuit or a signal line driver circuit, see FIG.2) is composed of polycrystalline silicon. That is, the driver circuitsection 4 is an integrated driver circuit that is simultaneouslyconstructed during the production process for the liquid crystal displayunit.

The liquid crystal display unit comprises a plurality of scanning linesand a plurality of signal lines arranged in a matrix, and thin filmtransistors (TFT), serving as pixel switching elements, disposed at eachintersectional position of the scanning lines and the signal lines. Thedriver circuit section 4 is formed in a peripheral portion of the liquidcrystal display unit.

The driver circuit section 4 comprises a plurality of circuit elements20 including an inverter and a latch, and to each of the circuitelements 20, electric power is independently supplied via anindividually-wired line array 21 comprising a plurality of power supplylines 7. Each of electrode pads 22 of the individually-wired line array21 is extended to the peripheral portion of the array substrate 2. It isto be noted that the individually-wired line array 21 is provided for aset of power supply lines 7 as well as for the data lines and clocksignal lines, or various other control signal lines, and these lines arecommonly connected to the corresponding bus lines 12 and are connectedto an external circuit via a connecting terminal 13. For convenience indescription, taking the power supply lines 7 as an example, furtherdetails are given below.

A notable feature here is that a multi-layer bus line-equipped section5, which has a bus line to be commonly connected to theindividually-wired line array 21, is formed in a peripheral portion ofthe array substrate 2, and that by the multi-layer bus line-equippedsection 5, each of the electrode pads 22 of the individually-wired linearray 21 is connected to the bus line 12 and is connected to a flexiblewiring board 6 via the connecting terminal 13 of the bus line 12. Thisconfiguration achieves a low resistance in the bus line 12 and a sizeand thickness reduction in the flexible wiring board 6.

The specific configuration of the bus line-equipped section 5 is shownin FIGS. 2 and 3. The bus line-equipped section 5 is composed of a resinsubstrate 10, which has an extended shape (extended in a lateraldirection of FIG. 1) and is mounted on the peripheral portion of thearray substrate 2. The resin substrate 10 has an insulating layer 11composed of, for example, aramid-epoxy resin, and on the upper surfaceof the insulating layer 11, the bus line 12 is formed. The bus line 12is produced by patterning a copper foil formed on the upper surface ofthe insulating layer 11 in a prescribed pattern. The bus line 12 isprotected by a protective layer 18.

In the insulating layer 11, via holes 17 are formed, and in each of thevia holes 17, an electrically conductive member 14 mainly composed of anelectrically conductive paste is filled. At the lower end of theelectrically conductive member 14, a bump electrode 15 is formed, andthe bump electrode 15 is bonded with each of electrode pads 22 by meansof a conductive adhesive 16. This ensures the securing of the resinsubstrate 10 with the array substrate 2 and the electrical connection ofthe individually-wired line array 21 with the bus line 12. It is to benoted that the protective layer 18 also has a via hole 17 formedtherein, and in this via hole 17, a conductive paste is filled, forminga connecting terminal 13 to an external circuit. The connecting terminal13 is connected to a wiring line 19 of a flexible wiring board 6 via aconductive adhesive 25, and the flexible wiring board 6 is folded andguided to the back side of the array substrate and is connected to aprinted circuit board having an external circuit formed thereon.

By employing such a configuration as described above, the bus line 12 isformed on the resin substrate 10 and therefore has a sufficient linewidth and a sufficient line thickness (film thickness). Accordingly, thebus line 12 has a low resistance.

In addition, the bus line 12 is taken out of the array substrate 2 fromone point, via the connecting terminal 13, and therefore, the size andthickness of the flexible wiring board 6 to be connected to theconnecting terminal 13 can be smaller than those of the prior artdevices, thus achieving size and thickness reduction of the displaydevice.

The protective layer 18 is not an essential element in the presentinvention, and therefore the protective layer 18 may be omitted.

EXAMPLE 1-2

FIG. 4 shows a cross-sectional view of a display panel according toExample 2. Example 1-2 is similar to Example 1-1 above, and likereference numerals refer to like parts. Example 1-2 is characterized inthat, in place of using a printed circuit board on which the flexiblewiring board 6 and the external circuit are mounted, the externalcircuit is directly mounted on the resin substrate. Specifically, asemiconductor chip 30 of a controller and the like is mounted on theresin substrate 10, and the semiconductor ship 30 is electricallyconnected to the connecting terminal 13. Such a configuration makes itpossible to eliminate the printed circuit board on which the flexiblewiring board 6 and the external circuit are mounted, thus remarkablyreducing manufacturing cost.

EXAMPLE 1-3

The semiconductor chip 30 can be buried in the via hole 17. Thisachieves a further planar surface of the resin substrate 10 incomparison with that of Example 1-2.

EXAMPLE 1-4

FIG. 6 shows a cross-sectional view of a display panel of Example 1-4.Example 1-4 is similar to Example 1-1, and like reference numerals referto like parts. Example 1-4 employs a film substrate 40 havingflexibility in place of the resin substrate 10. The film substrate 40 iscomposed of, for example, a resin mainly composed of polyimide or epoxy.Consequently, bonding of the resin substrate 40 with the array substrate2 can be carried out in such a manner that the film-like resin substrate40 is gradually attached to the array substrate 2 from one end of thefilm-like resin substrate to another, which makes it easy to align theelectrode pad 22 and the bump electrode 15.

In addition, the film substrate 40 may be composed of a thermoplasticmaterial. In this case, the film substrate 40 itself has semi-adhesiveproperty, and consequently, the film substrate 40 can be directly bondedto the array substrate 2, eliminating the bump electrode 15 and theconductive adhesive 16. When the film substrate 40 has semi-adhesiveproperty, attachment and detachment of the substrate can be repeatedagain and again, which makes it easy to carry out an alignment processof the electrode pads 22 and the conductive members 14 in the via holes17 and increases the precision of the alignment.

EXAMPLE 1-5

FIG. 7 shows a cross-sectional view of a display panel of Example 1-5.In Example 1-5, in place of the single layer resin substrate 10, amulti-layer substrate 50 is employed. Specifically, as shown in FIG. 7,the multi-layer substrate 50 has a bus line 12 on the surface of theuppermost layer as well as on the surface of an inner layer, and theupper and lower bus lines are selectively connected via via holes 17formed in each layer, forming a three-dimensional wiring line structure.This configuration allows more freedom in designing the bus line 12 andmakes it possible to easily arrange a plurality of bus lines 12depending on the types of signal lines. For example, when a plurality oftypes of individually-wired line arrays 21 are to be connected to aplurality of corresponding bus lines 12, there are instances where oneof the bus lines 12 intersects another bus line 12. In such an instance,this example is particularly effective for easy formation of the buslines.

SUPPLEMENTARY REMARKS FOR EXAMPLES 1-1 to 1-5

(1) In the foregoing examples, the conductive adhesive 16 may be ananisotropic conductive film or a silver paste.

The conductive adhesive 16 may be made of a material havingthermoplastic property. In such a case, the resin substrate and thearray substrate can be repeatedly bonded and detached many times, sothat the alignment of the resin substrate and the array substrate iseasily carried out. This is possible in the following manner: after anadhesive is semi-cured, an alignment compensation of the resin substrateand the active matrix substrate is carried out, and the adhesive iscured at, for example, 120–150° C. to secure the resin substrate and theactive matrix substrate.

(2) Although the examples above employ bump electrodes 15, in place ofthe bump electrodes 15, the device of the invention may have aconfiguration such that a lower end of the conductive member 14protrudes from the via hole and the protruding portion is directlyconnected to the electrode pad 22.

(3) The present embodiment describes a liquid crystal display device asan example, but the present invention is similarly applicable to adisplay device having a light emission type matrix panel, such as plasmadischarge panels (PDP) and electro-luminescent (EL) displays.

Embodiment 2

In Embodiment 1, a resin substrate having a bus line is mounted on aperipheral portion of the array substrate. In Embodiment 2, the bus lineis formed by printing. In Embodiment 2, the liquid crystal displaydevice is an integrated driver circuit type liquid crystal displaydevice in which the driver circuits are composed of a polycrystallinesilicon semiconductor layer, as in Embodiment 1.

First, referring to FIGS. 8(A) and 8(B) and FIG. 9, the principle ofEmbodiment 2 is discussed, and thereafter, various examples aredetailed.

FIG. 8(A) shows a plan view of a liquid crystal display device ofEmbodiment 2, FIG. 8(B) shows a cross-sectional view of the liquidcrystal display device of Embodiment 2, and FIG. 9 shows an enlargedcross-sectional view of FIG. 8(B).

FIGS. 8(A), 8(B), and 9 show an array substrate 101 on which thin filmtransistors are formed, a counter substrate 102, a flexible wiring board103 for the connection with an external circuit, a multi-layer wiringline-equipped section 104 for a bus line, an anisotropic conductionresin 105 for connecting the flexible wiring board and the bus line, aninterlayer insulating film 106, a sealant 107 for sealing the gapbetween the array substrate and the counter substrate, a bus line 108, avia hole 109, and a thin film wiring region 110 including thin filmtransistors provided on the array substrate.

One of the important features in the present embodiment is as follows.As shown in FIG. 9, the interlayer insulating film is formed on the thinfilm wiring region including thin film transistors provided on the arraysubstrate, and thereafter the bus line is printed in only a requiredposition/positions with the use of a conductive paste. Thereby, amulti-layer wiring connection is realized on the array substrate, and byremarkably reducing the size of the flexible wiring board and theprinted circuit board, size reduction in the liquid crystal displaydevice is achieved.

Now, specific configurations and producing methods are detailed by wayof examples.

EXAMPLE 2-1

FIGS. 10(A) to 10(C) show cross-sectional views illustrating the majorsteps in the process of producing a liquid crystal display device ofExample 2-1.

In FIGS. 10(A) to 10(C), reference number 121 designates a transparentinsulating substrate, for which the present example employed a glasssubstrate available from Corning Inc. Reference number 122 designates anundercoat film, for which in the present example, an SiO₂ film having athickness of about 400 nm was formed by plasma CVD. Reference number 123designates a polysilicon film, for which the present example employed apolysilicon film produced by first forming an amorphous silicon film andsubsequently fusing the film by an excimer laser. Reference number 124designates a gate insulating film, for which, in the present example, anSiO₂ film having a thickness of about 90 nm was formed by plasma CVD.Reference number 125 designates a gate electrode, for which, in thepresent example, a Mo—W alloy film was formed by sputtering. Referencenumber 126 designates a pixel transistor, which includes the polysiliconfilm 123, the gate insulating film 124, and the gate electrode 125. Itis noted that the device of FIGS. 10(A) to 10(C) includes p-typetransistors and n-type transistors for the driver circuit, which areformed in a similar configuration.

Reference number 127 designates an interlayer insulating film, forwhich, in the present example, an SiO₂ film having a thickness of about400 nm was formed by plasma CVD. Reference number 128 designates aprotective film, for which, in the present example, an SiN_(x) filmhaving a thickness of about 500 nm was formed by plasma CVD. Referencenumber 129 designates a planarizing film, for which, in the presentexample, a photosensitive acrylic-based material having a thickness ofabout 3 μm was formed by coating. Reference number 130 designates atransparent conductive film, for which, in the present example, an alloyfilm of indium and tin having a thickness of about 75 nm was formed.Reference number 108 designates a bus line, for which the presentexample employed a bus line formed by screen printing using a silverpaste DD-1662B-69 available from Kyoto Elex Co., Ltd. Reference number132 designates a printed protective film for protecting the bus line108, for which the present example employed a film formed by screenprinting using an acrylic-based resin. Reference number 133 designates asource/drain electrode, for which, in the present example, a Ti/Aldouble layer film was formed by sputtering.

Now, an example of the producing method of the present embodiment isdiscussed below.

As shown in FIG. 10(A), an array substrate including a pixel portion isproduced in a similar manner to a conventional method, except that, whena pattern of the protective film is formed, a via hole 109 issimultaneously formed by etching a wiring electrode portion (whichcorresponds to an electrode pad) in the thin film wiring regionincluding the driver circuit section, for the connection with anexternal circuit.

Thereafter, as shown in FIG. 10(B), a bus line 108 is screen printed andcured at 180° C. for 30 minutes. Subsequently, as shown in FIG. 10(C),in order to protect the bus line 108, a printed protective film 132 isformed by screen printing.

Thus, a multi-layer wiring line-equipped section 104 for a bus line isformed on the array substrate.

The bus line formed in the present example had a sheet resistance ofabout 0.02 m Ω/□ and a printed width of 100 μm, and therefore achieved asufficiently low resistance for a signal line and a power supply line.The present example uses the protective film 128, which hasconventionally been used for an array substrate, as an interlayerinsulating film in the multi-layer wiring line-equipped section 104, andtherefore achieves simplification in the producing method since it isunnecessary to form an additional interlayer insulating film.

EXAMPLE 2-2

FIG. 11(A) to 11(C) show the major steps in the process of producing aliquid crystal display device of Example 2-2. In the present exampletoo, a glass substrate available from Corning Inc. was employed as theglass substrate 121, and an SiO₂ film of about 400 nm was formed as theundercoat film by plasma CVD. The figures show a polysilicon film 123, agate insulating film 124, and a gate electrode film 125, and these arecomprised in a pixel transistor 126. In the driver circuit section,p-type and n-type transistors and a thin film wiring region comprisingvarious wiring lines are provided. The figures also show an interlayerinsulating film 127, a protective film 128, a transparent conductivefilm 130, a bus line 108, and a source or a drain electrode 133. Thesewere produced in the same manner and in the same thicknesses as those inExample 2-1, and therefore, specific details are not further elaboratedon here. Reference number 34 designates a printed interlayer insulatingfilm, for which, in the present example, a polyimide-based resin wasscreen printed and cured at 300° C. for 20 minutes.

Now referring to each of the cross-sectional views, the producing methodis discussed below.

As shown in FIG. 11(A), when the protective film 128 is patterned, thevia hole 109 is simultaneously formed by an etching process, andthereafter, the transparent conductive film 30 is formed and patternedover a pixel region of the protective film 128 in a prescribed shape.

Next, as shown in FIG. 11(B), the printed interlayer insulating film 134is formed over the thin film wiring line region including the drivercircuit section by printing. The film thickness of the printedinterlayer insulating film 134 was about 15 μm. In the printing, patternaligning is required so that the via hole portion of the protective film128 approximately matches the via hole portion to be formed by theprinting. Subsequently, as shown in FIG. 11(C), the bus line is printedby screen printing, which completes the process.

In a liquid crystal display device thus produced, the bus line, in whicha large current flows, and the driver circuit section, in which thinfilm transistors are present, are separated by forming a 15-μm thickpolyimide having a low dielectric constant. Therefore, adverse effectscaused by electromagnetic field were avoided, and the liquid crystaldisplay device thus produced was suitable for high speed driving.

EXAMPLE 2-3

FIG. 12(A) to 12(C) show the major steps in the process of producing aliquid crystal display device of Example 2-3. In the present exampletoo, the liquid crystal display device was produced by the same process,including that for thin film transistors, as that in Example 2-1 above.In the figures, there are shown a glass substrate 121, for which thepresent example employed a glass substrate available from Corning Inc.,an undercoat film 122, a polysilicon film 123, a gate insulating film124, and a gate electrode 125, and the polysilicon film 123, the gateinsulating film 124 and the gate electrode 125 forms a pixel transistor126. The figures also show an interlayer insulating film 127, aprotective film 128, a planarizing film 129, a transparent conductivefilm 130, a bus line 108, a printed protective film 132, and a source ora drain electrode 133.

Now referring to the cross-sectional views, the producing method isdiscussed. As shown in FIG. 12(A), in the protective film 128, the pixelregion including a position to be connected to the bus line 108 of thedriver circuit section is subjected to a photolithography process and anetching process to form the via hole 109. Thereafter, the planarizingfilm 129 is formed to have a thickness of about 5 μm, and is subjectedto photolithography and etching to form the via hole 109 in a likemanner. In this process, of course, the pattern is formed so that theportion to be connected to the bus line 108 of the driver circuitsection is opened. Subsequently, ITO (indium tin oxide), serving as thetransparent conductive film 130, is formed by sputtering, and thecontacts with the pixel portion and the driver circuit section areformed.

Next, as shown in FIG. 12(B), the bus line is printed by screenprinting. Thereafter, as shown in FIG. 12(C), in order to protect thebus line 108, an acrylic-based resin is screen printed to form theprinted protective film 132, which completes the producing of a liquidcrystal display device.

In the present example, the planarizing film, which is formed forincreasing an aperture ratio, is used as the interlayer insulating filmfor the bus line 108, and the transparent conductive film is used forthe contacts with the connecting electrode of the driver circuitsection. Therefore, the bus line need not to be in a direct contact withthe connecting electrode of the driver circuit section, and the viaholes can be made sufficiently small by a photolithography process,which makes it possible to achieve a further device size reduction and areliable contact with the connecting electrode.

In the present embodiment, a liquid crystal display device having a topgate structure is taken as an example, but the embodiments of thepresent invention are not limited to those with a top gate structure,and of course, are similarly applicable to those with a bottom gatestructure.

In addition, although a silver paste is given as an example of amaterial for the bus line, various conductive materials, such as copper,gold, and alloys thereof, may be used insofar as the material can becured at about 400° C. or lower and has a sheet resistance of about 0.05m Ω/□ or lower.

In addition, although screen printing is given as an example, theprinting technique is not limited to screen printing, and variousprinting techniques may be employed, such as a writing technique, anintaglio printing technique, and an ink-jet printing technique.

In addition, materials for the printed interlayer insulating film arenot limited to polyimide-based materials, and various materials may beused insofar as the materials can be cured at 400° C. or lower and beformed by printing or coating, such as an acrylic-based photosensitiveresin and the like.

Additionally, in the present embodiment, a technique for producing amore reliable liquid crystal display device by forming a printedprotective layer for protecting a bus line has been described, but it isnoted that this is not an essential element in the present invention.

The present embodiment describes a liquid crystal display device as anexample, but the present invention is similarly applicable to a displaydevice having a light emission type matrix panel, such as plasmadischarge panels (PDP) and electro-luminescent (EL) displays.

Embodiment 3

Embodiment 3 is characterized in that a bus line is buried in an activematrix substrate. Specific configurations of Embodiment 3 are detailedin the following Examples 3-1 to 3-6.

EXAMPLE 3-1

FIG. 13 shows a plan view of a liquid crystal display device of Example3-1, and FIG. 14 shows a circuit diagram of the liquid crystal displaydevice. The device discussed Example 3-1 is a 12.1-inch liquid crystaldisplay device having 1024×768 pixels (so-called XGA mode) in which thepixel size is 57 μm square and analog image signals representing red,green, and blue are inputted for displaying color images. The liquidcrystal display device of Example 3-1 is an integrated driver circuittype liquid crystal display device in which the driver circuit iscomposed of a polycrystalline silicon semiconductor layer.

As shown in FIG. 13, the liquid crystal display device has an activematrix substrate 212, a counter substrate 213, a liquid crystal layer211 disposed between the substrates 212 and 213, polarizing plates 214and 215 each disposed on one side of each of the substrates 212 and 213,and a back light 216 disposed outside the polarizing plate 214. Thecounter substrate 213 is a glass substrate. On the inner surface of thecounter substrate 213, a micro color filter 217 and a counter electrode218 are formed. The active matrix substrate 212 comprises, on a glasssubstrate 210, a liquid crystal display unit 221 having a matrix arraycomposed of thin film transistors, and driver circuits 224–226 fordriving the liquid crystal display unit 221, which are also formed on aglass substrate 210. More specifically, the liquid crystal display unit221 of the active matrix substrate 212 comprises pixel switching thinfilm transistors (TFTs) 222 and pixel electrodes 223, eachcorrespondingly provided for each pixel. The driver circuits 224–226 areprovided on a peripheral portion of the liquid crystal display unit 221.

The driver circuit 224 comprises, as shown in FIG. 14, a shift register231 and a buffer 232, and is connected to the gate electrode of each TFT222 via a scanning signal line (gate line) 233. The driver circuit 224sequentially outputs a scanning signal pulse to each scanning signalline 33 in response to a clock signal CLx, a inverted clock signal CLx*,and a start pulse (vertical synchronizing signal) STv.

The driver circuit 25 comprises four sets of shift registers 234–237, abuffer 238, and an analog switch (transfer gate) 239, and applies animage signal voltage to each of odd-numbered pixel electrodes 223 withrespect to the horizontal direction in the display panel, via an imagesignal line 240 (source line) and the pixel switching TFT 222. Thedriver circuit 226 has a similar configuration to that of the drivercircuit 225, and applies an image signal voltage to each ofeven-numbered pixel electrodes 223 via an image signal line 241. Sincethe driver circuit 226 has a similar configuration to that of the drivercircuit 225 and operates in a similar manner, the driver circuit 225 ischiefly explained in the following discussion and the driver circuit 226is not further detailed here.

Each of the shift registers 234–237 in the driver circuit 225 iscomposed of, as shown in FIG. 15, a plurality of passgates (three-statebuffers) 242 and inverters 243. The shift registers 234–237 sequentiallyoutput, as shown in FIG. 16, pulse signals each having a pulse width of200 ns and being phase shifted by 50 ns (each overlapped by 150 ns) inresponse to clock signals CL1–CL4, inverted clock signals CL1*–CL4*, andstart pulses (horizontal synchronizing signals) STh.

The analog switch 239 outputs image signal voltages received from analogimage signal lines D0–D2 to image signal lines 240 in response to thepulse signals received from the shift registers 234–237. From the shiftregisters 234–237, the pulse signals each overlapped by 150 ns areoutputted as mentioned above, and in the overlapped period, an identicalimage signal is outputted from the analog switch 239 to each set of fourimage signal lines 240. Thus, each gap between the pixel electrodes andthe counter electrodes 218 is first precharged during the period of 150ns, and thereafter, in each gap, an electric charge corresponding to animage signal to be outputted is stored during the remaining period of 50ns. This means that because the driver circuit has four stages of shiftregisters, a writing time of 200 ns can be practically obtained atsubstantially the same speed (a constant frame period) as that in thecase where the dot clock is 50 ns. Therefore, reliable writing of imagesignals is ensured even when the number of pixels is large.

In addition, a +V power supply line 251 and a −V power supply line 252,which are bus lines for supplying power supply voltage to the drivercircuit 225, are buried in the glass substrate 210. It is noted that a+V power supply line 253 and a −V power supply line 254, which are buslines for the driver circuit 226, are also buried in the glass substrate210. In the following discussion, the term “power supply line” does notmean an individually-wired line array for supplying power to eachcircuit element, but means a bus line commonly connected to theindividually-wired line array.

In the present example, the power supply line for the driver circuit 224does not have a buried wiring structure because voltage drop in thedriver circuit 224 does not cause as serious a problem as that in thedriver circuits 225 and 226. However, it is of course preferable thatthe power supply line for the driver circuit 224 also have a buriedwiring structure.

That power supply lines have a buried wiring structure is the primaryfeature of the present embodiment. Now referring to FIGS. 18–21, theburied wiring structure is detailed below.

FIG. 18 shows a schematic plan view of the active matrix substrate 212,FIG. 19 shows a cross-sectional view taken along the line X1—X1 in FIG.18, FIG. 20 shows a cross-sectional view taken along the line X2—X2 inFIG. 18, and FIG. 21 shows a cross-sectional view taken along the lineX3—X3 in FIG. 18.

The glass substrate 210 has recessed grooves 260, 261 and 262, 262 inopposing peripheral portions thereof, respectively. The recessed grooves260 and 261 are linearly extended near the driver circuit 225, and therecessed grooves 262 and 263 are linearly extended near the drivercircuit 226. In the recessed groove 260, a metal wiring line serving asthe +V power supply line 251 is buried, and in the recessed groove 261,a metal wiring line serving as the −V power supply line 252 is buried.In the recessed groove 262, a metal wiring line serving as the +V powersupply line 253 is buried, and in the recessed groove 263, a metalwiring line serving as the −V power supply line 254 is buried. The +Vpower supply line 251 is connected to the driver circuit 225 (to beprecise, connected to power supply electrode pads of the driving circuit225) via connecting electrodes 266, and the −V power supply line 252 isconnected to the driver circuit 225 (to be precise, connected to powersupply electrode pads of the driving circuit 225) via connectingelectrodes 265, so that electric power is supplied to the driver circuit225. In a like manner, the +V power supply line 253 is connected to thedriver circuit 226 (to be precise, connected to power supply electrodepads of the driving circuit 226) via connecting electrodes 267, and the−V power supply line 254 is connected to the driver circuit 226 (to beprecise, connected to power supply electrode pads of the driving circuit226) via connecting electrodes 268, so that electric power is suppliedto the driver circuit 226. On the surfaces of the metal wiring lines, aninsulating layer 277 (see FIGS. 20 and 21) is formed to prevent contactbetween the connecting electrode 266 and the power supply line 252.Although not shown in the figures, such an insulating layer 277 is alsoprovided for the power supply lines 253 and 254 to prevent contactbetween the connecting electrode 67 and the power supply line 254.

It is also possible that the power supply lines 251 and 252 areconnected to power supply electrode pads 225 b and 225 a via theconnecting electrodes 266 and 265, respectively, in such a manner, asshown in FIG. 22, that the connecting electrodes 266 and 265 areextended from the same positions of the power supply lines 251 and 252.

As has described above, the power supply lines have a buried wiringstructure, and this achieves the following advantageous effects.

(1) If the film thickness of the metal wiring line layer is increased byincreasing the depth of the recessed groove, the wiring line resistanceof the power supply lines is easily made about 0.1 ohms. Consequently,even if a shoot-through current of about 160 mA flows in the shiftregisters 234–237 and so forth, voltage drop of power supply voltage isminimized to ensure reliable operation of the driver circuit 225. Forreference, in such cases that the resistance value is reduced by formingpower supply lines in thin film form, it is necessary that theperipheral region of the substrate have a large area, and therefore, aliquid crystal display device having a narrow frame cannot be achievedby such a technique. In this regard, the present embodiment can reducethe resistance value of power supply lines without increasing the areaof the peripheral region, and therefore makes it possible to produce aliquid crystal display device having a narrow frame.

(2) Even if the film thickness of the metal wiring lines is increased,power supply lines do not protrude from the surface of the substratebecause the metal wiring line layer is buried in the substrate.Accordingly, the wiring lines for connecting the metal wiring line layerto the driver circuit and the insulating layer formed thereover do nothave differences in the surface levels, and the surface of the activematrix substrate is planarized. Consequently, uniformity of the cell gapcan be maintained, and degradation of display characteristics does notoccur. For reference, in order to merely reduce the resistance value ofthe power supply lines, it is only necessary to form a metal wiring linelayer having a large film thickness on the substrate. However, in such acase, the metal wiring line layer greatly protrudes from the substratesurface, and this results in differences in the surface levels of thewiring lines connecting the metal wiring line layer and the drivercircuit and of the insulating layer formed thereover. This causes thefollowing problem; when the substrates are attached and pressed fromboth sides thereof to make the cell gap to be a constant value, a bendoccurs in the substrates and a uniform cell gap cannot be maintainedover the substrate plane. In this regard, since the present embodimentemploys a buried structure for the metal wiring line layer,planarization of the substrate surface is achieved, and uniformity inthe cell cap is maintained.

The film thickness of the metal wiring layer may be determined takinginto consideration the power supply voltages and the size of the liquidcrystal display panel.

Now, a producing method of the buried electrode structure is describedbelow.

(1) First, as shown in FIG. 23(1), a resist 270 is applied over theentire surface of the glass substrate 210, on which the driver circuits224–226 and the liquid crystal display unit 221 are formed.

(2) Next, as shown in FIG. 23(2), portions of the resist 270 whererecesses are to be formed in the glass substrate 210 are removed.

(3) Next, as shown in FIG. 23(3), using an aqueous solution containing2% hydrofluoric acid and 8% glycerin, etching is carried out for about 2minutes to form a recess having a depth of about 1500 nm. Subsequently,a metal film 75 composed of Al is formed by sputtering so as to have athickness of 1500 nm.

(4) Next, as shown in FIG. 23(4), the resist 270 is removed. Thereby,metal wiring lines 276, corresponding to power supply lines 251–254, areformed in such a state that the wiring lines are buried in the recessedgrooves 260–263.

(5) Next, by a photolithography method, the insulating film 277 andcontact holes 278 are formed as shown in FIGS. 20 and 21, and theconnecting electrodes 265–268 for connecting the buried metal wiringlines and the driver circuit are formed. Thus, an active matrixsubstrate 212 in which power supply lines 251–254 are buried isproduced.

It is noted that metal materials to be buried may be various materialssuch as Ni, Cr, Mo, and Ta, other than Al.

EXAMPLE 3-2

A producing process of Example 3-2 is discussed. The basic circuitconfiguration and the process of making TFTs on a glass substrate areidentical to those in Example 3-1, except the following. In Example 3-1,the recessed grooves are formed by chemical etching, but in Example 3-2,the recessed grooves are formed by sandblasting. Now, referring to FIGS.24(1) to 24(6), details are given below.

(1) First, as shown in FIG. 24(1), a resist 270 is applied over theentire surface of the glass substrate 210, on which the driver circuits224–226 and the liquid crystal display unit 21 are formed.

(2) Next, as shown in FIG. 24(2), portions of the resist 270 whererecesses are to be formed in the glass substrate 210 are removed.

(3) Next, as shown in FIG. 24(3), using the resist 270 as a mask,etching by sandblasting is carried out for about 2 minutes. Thereby, theportions in the glass substrate which are not covered by the resistpattern are caved in by blasted hard particles, and recesses having adepth of about 1500 nm (corresponding to recessed grooves 260–263) areformed.

(4) Next, as shown in FIG. 24(4), a metal film 275 composed of Al isformed by sputtering, so as to have a thickness of 1500 nm.

(5) Next, as shown in FIG. 24(5), the resist 270 is removed. Thus, metalwiring lines 276 corresponding to the power supply lines 251–254 areformed in such a state that the metal wiring lines 276 are buried in therecessed grooves 260–263.

(6) Next, by a photolithography method, the insulating film 277 andcontact holes 278 are formed as shown in FIGS. 20 and 21, and theconnecting electrodes 265–268 for connecting the buried metal wiringlines and the driver circuit are formed. Thus, an active matrixsubstrate 212 in which power supply lines 251–254 are buried isproduced.

Example 3-2 has such an advantage that, since the recessed grooves areformed by sandblasting, the etching rate is 10 or more times higher thanthat of Example 3-1, in which the recessed grooves are formed by usingan etchant solution, which indicates that the processing speed is high.In terms of the precision of the processing, Example 3-1 is superior toExample 3-2. Accordingly, the chemical etching method of Example 3-1exhibits a high controllability of the depth of the recessed groove, andit is possible to control the depth to a desirable depth. Therefore, itis desirable that when a reduction in the time required for theproducing process is considered more important, a physical etchingmethod as Example 3-2 is employed, whereas when a precision in the depthof the recessed grooves is considered more important, a chemical etchingmethod as Example 3-1 is employed.

EXAMPLE 3-3

FIGS. 25 shows a schematic cross sectional view of an active matrixsubstrate of Example 3-3. The foregoing Examples 3-1 and 3-2 depict atechnique in which the glass substrate is directly processed by etchingor sandblasting. By contrast, in Example 3-3, the glass substrate 210 isnot processed, but instead, a resin 280 is applied onto the substratesurface and metal wiring lines 276 are buried in the resin 280. It isnoted that, between the driver circuit 225 and the metal wiring lines276, which correspond to the power supply line 252, an insulating layer(not shown in FIG. 25) is provided, and via the connecting electrode 265(not shown in FIG. 25) passing through a contact hole formed in theinsulating layer, the power supply line 252 is connected to the drivercircuit 225. On the surfaces of the metal wiring lines 276, 276, whichcorrespond to the power supply lines 252 and 251, an insulating layer(not shown in FIG. 25) is formed, and via the connecting electrode 266(not shown in FIG. 25) passing through a contact hole formed in theinsulating layer, the power supply line 251 is connected to the drivercircuit 225. These configurations for the power supply lines 252 and 251are also provided for the power supply lines 253 and 254. As aconsequence, contact between the connecting electrode 266 and the powersupply line 252 is prevented, and likewise, contact between theconnecting electrode 267 and the power supply line 254 is prevented.

This configuration of a buried wiring structure can also reduce theresistance values of the power supply lines 251–254, and in addition,because the resin layer 280 serves as a planarizing layer, a uniformcell gap can be maintained. It is noted that Examples 3-4 to 3-6, aswell as the present Example 3-3, have a structure such that a resinlayer is formed on a glass substrate, and in the resin layer, metalwiring lines, which form power supply lines, are buried. Therefore, inExamples 3-4 to 3-6 as well, the resistance values of the power supplylines are reduced, and in addition, a uniform cell gap can be achieved.

Now, a producing method of the buried wiring structure is specificallydescribed with reference to FIG. 13.

(1) First, as shown in FIG. 26(1), an active matrix pattern(corresponding to the liquid crystal display unit 221) including pixelelectrodes, and a peripheral pattern (driver circuits 224–226) areformed, and thereafter, a photosensitive acrylic resin 280 is applied onthe entire surface of the glass substrate 210 by, for example, spincoating, so as to have a film thickness of 1500 nm.

(2) Next, as shown in FIG. 26(2), by carrying out exposure and alkalinedevelopment, a pattern is formed so that grooves for common wiring linesincluding power supply lines are formed in the periphery of the drivercircuit sections. The entire substrate is exposed (g, h, or i ray lightsource at 300 mJ) to bleach the photosensitive acrylic resin to make ittransparent. The g, h, or i rays refer to bright line spectrums of amercury lamp for exposure each having a certain wavelength. Consideringthe efficiency, it is preferable to use i rays, which exhibits thestrongest energy.

(3) Next, as shown in FIG. 26(3), a metal layer 75 composed of Al, whichis to be buried in the resin 280, is formed by sputtering, so as to havea thickness of 1500 μm.

(4) Next, as shown in FIG. 26(4), the etching is removed so that thedeposited metal layer 275 remains as a common electrode wiring patternincluding power supply and as a pattern for connecting to the drivercircuit. Then, the connecting electrodes 265, 266 and 268, 267 and theinsulating layers relating to the connecting electrodes 265, 266 and268, 267 are formed. Thus, an active matrix substrate 212 in which thepower supply lines 251–254 are buried in the resin 280 is produced.

According to the above-described producing process, it is unnecessary toetch the glass substrate 210, and therefore, precision of the processingis further improved, and controllability of the thicknesses of metalwiring lines formed as buried electrodes is also improved.

EXAMPLE 3-4

FIGS. 27(1) to 27(3) illustrate a producing process of an active matrixsubstrate of Example 3-4. In Example 3-4, the peripheral wiring patternis formed by screen printing. Specific details of the producing processare as follows.

(1) First, as shown in FIG. 27(1), an active matrix pattern includingpixel electrodes (liquid crystal display unit 221) and a peripheralpattern for driving the liquid crystal panel (driver circuits 224–226)are formed on the glass substrate 210, and thereafter, for a commonwiring section including power supplies, an electrically conductivethermosetting resin is screen printed to form a metal layer 276A thatcorresponds to the power supply lines 252 and 254 and to the connectingelectrodes 265 and 268. Next, an insulting layer (not shown) is formedon the metal layer 276A, and subsequently, a metal layer 276A thatcorresponds to the power supply lines 251 and 253 and to the connectingelectrodes 265 and 268. This prevents a portion of the metal layer 276Acorresponding to the connecting electrode 266 from making contact with aportion of the metal layer 276A corresponding to the power supply line252. Likewise, this also prevents a portion of the metal layer 276Acorresponding to the connecting electrode 267 from making contact with aportion of the metal layer 276A corresponding to the power supply line254.

(2) Next, as shown in FIG. 27(2), after the screen printing, theconductive resin 276A is heated at a temperature of 150–180° C. to curethe resin. The temperature for curing the resin should be adjusteddepending on types of the resin.

(3) Next, as shown in FIG. 27(3), after the wiring lines have beenformed, an insulative resin 280 is similarly screen printed so as to beburied between the wiring lines, in order to planarize the surface.

By employing a screen printing method as described above, the timerequired for forming a pattern is reduced. In addition, the costs forproducing apparatuses are very low in comparison to a photolithographymethod, and therefore, this technique is particularly suitable for suchcases with a long power supply line, such as an active matrix substratefor large-sized liquid crystal display panels. Although not superior toa photolithography method in terms of the precision of the processing,this technique is effective for wiring patterns that do not require highprecision such as those for power supply lines.

The forming of a planarizing film may be carried out by a spin coatingmethod, other than the screen printing. Thus, the above-describedprocess makes it possible to easily form wiring lines having a thicknessof 1 μm or larger.

EXAMPLE 3-5

FIG. 15 illustrates a producing process of an active matrix substrate ofExample 3-5. In Example 3-5, a metal fine wire 281 is used for thematerial of the metal wiring lines, and the metal fine wire is buried.In the present example, the diameter of the metal fine wire is 50 μm.

Specific details of the producing process are as follows.

(1) First, as shown in FIG. 28(1), an active matrix pattern includingpixel electrodes (liquid crystal display unit 221) and a peripheralpattern for driving the liquid crystal panel (driver circuits 224–226)are formed on the glass substrate.

(2) Next, as shown in FIG. 28(2), metal fine wires 281, corresponding topower supply lines, each having a diameter of 50 μm are formed in theperipheral portion of the glass substrate 210.

(3) Next, as shown in FIG. 28(3), connecting electrodes 265–268 forconnecting the metal fine wires 281 and the driver circuits 225, 226 areformed. Between the connecting electrode 266 and the metal wiring line281 corresponding to the power supply line 252, an insulating layer isformed, and likewise, between the connecting electrode 268 and the metalwiring line 281 corresponding to the power supply line 251, aninsulating layer is formed.

(4) Next, as shown in FIG. 28(4), an insulative resin 280 is screenprinted so as to be buried between the wiring lines, in order toplanarize the surface.

It is noted that in addition to a screen printing method, a spin coatingmethod may be employed to form a planarizing film.

In addition, as shown in FIG. 29, the power supply lines 251 and 252 areconnected to the power supply electrode pads 225 a and 225 b via theconnecting electrodes 265 and 266 in such a manner as shown in FIG. 29that the connecting electrodes 265 and 266 are extended from the samepositions of the power supply lines 251 and 252.

Suitable materials for the metal fine wiring line 281 include Ti, Cr,and gold, and, when such materials are employed, further reduction inthe resistance values is possible.

As is described above, Example 3-5 eliminates the step of forming awiring pattern by employing pre-formed metal fine wires, reducing thenumber of production steps. In addition, by varying the diameter of themetal fine wires, the resistance value of a power supply line can bedetermined. Accordingly, by selecting a metal fine wire having apredetermined resistance value, a desired resistance value can beobtained. Therefore, alterations of the resistance value are easy.Furthermore, the production cost is low.

EXAMPLE 3-6

FIGS. 30(1) to 30(3) illustrate a production process of an active matrixsubstrate of Example 3-6. In Example 3-6, a thick film for bus lines isformed on a peripheral region of the glass substrate 210 on which anactive matrix array is formed, using a plating process. By using aplating process, a layered wiring line structure including a lowresistance metal can be formed, and as a result, further reduction inthe power supply line resistance is achieved. It is noted that, betweenthe driver circuits 225, 226 and the portions of the copper foil layer290 disposed to be the lowermost layer of the metal wiring thick filmwhich corresponds to the power supply lines 252 and 254, an insulatinglayer in which the portions corresponding to the connecting electrodes265 and 268 are incised (not shown) is interposed. On a gold-nickelplating layer 292, which is positioned to be the uppermost layer of themetal wiring thick film, an insulating layer (not shown) is formed. Theinsulating layer on the portions of the nickel plating layer 292 thatcorrespond to the power supply lines 251 and 253 has contact holesformed therein, and via the contact holes, the connecting electrodes 266and 267 are connected to the driver circuits 225 and 226. Thus, theconnecting electrodes 266 and 267 are prevented from making contact withthe portions of the gold-nickel plating layer 292 which correspond tothe power supply lines 252 and 254.

Specific details of the production method are as follows.

(1) First, as shown in FIG. 30(1), an active matrix pattern includingpixel electrodes (liquid crystal display unit 221) and a peripheralpattern (driver circuits 224–226) are formed on a glass substrate 210.

(2) Next, as shown in FIG. 30(2), a copper foil layer 290, a copperplating layer 291, and a gold-nickel plating layer 292 are layered toform a metal wiring line layer 276 having a thickness of, for example, 1μm or more, serving as a common wiring line section including powersupply lines. Specifically, using a photolithography method, a resistpattern is formed except on the portions where an undercoat metal is tobe formed. Next, a copper thin film, serving as an undercoat metal, isformed. Next, by lift off, unnecessary portions are removed. Next, usingthe remaining copper thin film as an undercoat layer, the substrate isdipped in a plating bath of a solution mainly composed of copper sulfateso that copper is plated on the undercoat thin film in a self-alignablemanner. Thus, a copper plating layer 291 is formed on the copper foillayer 290. Further, using a like plating method, a gold-nickel platinglayer 292 is formed on the copper plating layer 291.

(3) Next, after the connecting electrodes 266 and 267 (not shown), aninsulating layer (not shown), and so forth have been formed, as shown inFIG. 30(3), an insulative resin 280 is screen printed between the wiringlines to planarize the surface.

Suitable materials for the plating include, other than the examplesmentioned above, nickel plating, chromium plating, and aluminum plating.The plating of alloys thereof is also possible.

In the present example, by employing a plating method, it is possible toform metal wiring lines on an undercoat metal film in a self-alignablemanner. In addition, for the metal to be formed on the undercoat metalfilm in a self-alignable manner, it is possible to employ a lowresistance metal such as gold, copper, or the like, and by selecting anappropriate undercoat metal, low resistance and high precision in themetal wiring lines can be achieved.

Supplementary Remarks for Examples 3-1 to 3-6

(1) In Examples 3-1 to 3-6 above, the buried wiring structure isemployed for the power supply lines, but the present invention is notlimited thereto, and the buried wiring structure is applicable to otherbus lines, such as data lines and clock lines for shift registers, inwhich signal delay caused by wiring line resistance is a problem.

(2) In Examples 3-1 to 3-4 above, the metal wiring layer may be formedin the following manner; a conductive layer composed of a thin film isformed beforehand, and on the conductive layer, metal wiring lines areformed by selective depositing. By doing so, metal wiring lines can beformed in a self-alignable manner as in the cases of the foregoingplating method, and it is possible to form low-resistance metal wiringlines by selecting a metal to be deposited. In the case of a selectivedepositing method, the process is carried out in a cleaner environmentthan in the case of a plating method. Therefore, impurities do not mixin the metal wiring lines, and the precision of the resistance value ofthe metal wiring lines is improved.

(3) The present embodiment describes a liquid crystal display device asan example, but the present invention is similarly applicable to adisplay device having a light emission type matrix panel, such as plasmadischarge panels (PDP) and electro-luminescent (EL) displays.

INDUSTRIAL APPLICABILITY

As has been described above, the present invention can sufficientlyaccomplish the objects of the invention. Specifically, the following areachieved.

(1) A resin substrate having a bus line is provided in a peripheralportion of an array substrate, and the bus line is connected to anindividually-wired line array, which is connected to a driver circuit,via a via hole in the resin substrate. This achieves the formation of alow resistance bus wiring line. In addition, a connecting terminal,which can be connected to an external circuit, is provided at a part ofthe bus line, which achieves a reduction in the sizes and thicknesses ofthe flexible wiring board or the printed wiring board.

(2) In addition to the above advantages, a multi-layer wiringline-equipped section for a bus line is provided on a thin film wiringregion including a driver circuit section composed of polycrystallinesilicon thin film transistors by printing, and thereby, the bus line canbe easily formed at desired regions.

(3) The bus lines for driver circuits have a buried wiring structure,and thereby wiring line resistance of power supply lines for applyingpower supply voltage to the driver circuits are easily reduced.Therefore, a shoot-through current in the semiconductor elements in thedriver circuits and a voltage drop caused by wiring line resistance ofthe power supply lines are minimized, which ensures a reliable operationof the device. Accordingly, a remarkable size reduction of theintegrated driver circuit section is possible, and a drivercircuit-integrated type liquid crystal display device having a narrowframe is realized.

1. A display device comprising: an active matrix substrate having aperipheral portion and a driver circuit section comprising a pluralityof circuit elements and a plurality of polycrystalline silicon thin filmtransistors; a counter substrate; a liquid crystal material filledbetween the active matrix substrate and the counter substrate; and anindividually-wired line array for supplying a clock signal, a datasignal or electric power to the plurality of circuit elements in thedriver circuit section, wherein the individually-wired line array isextended to the peripheral portion of the active matrix substrate,wherein: the peripheral portion of the active matrix substrate comprisesa multi-layer bus line-equipped section having a bus line located on theinsulator, the bus line is connected to the individually-wired linearray via the via hole, and the bus line comprises a connecting terminalfor connecting the display device to an external circuit; and theinsulator is a pre-formed resin substrate having a bus line located on asurface thereof and a via hole in the substrate.
 2. The display deviceaccording to claim 1, wherein the resin substrate comprising anaramid-epoxy resin.
 3. The display device according to claim 1, whereinthe via hole is filled with electrically conductive paste.
 4. Thedisplay device according to claim 1, wherein the resin substrate is amulti-layer structure comprising a plurality of layers in which said busline is located on a surface of an inner layer thereof as well as on asurface of the outermost layer thereof, and the bus lines areselectively connected to each other via a via hole in each of the layersto form a three-dimensional wiring structure.
 5. The display deviceaccording to claim 3, wherein the electrically conductive pastepartially protrudes from a lower opening of the via hole, and the activematrix substrate and the resin substrate are bonded together with theprotruding portion of the electrically conductive paste.
 6. The displaydevice according to claim 4, wherein an electrically conductive pastefills the via hole; the electrically conductive paste protrudes from alower opening of the via hole; and the electrically conductive pastepartially protrudes from the opening of the via hole, and the activematrix substrate and the resin substrate are bonded together with theprotruding portion of the electrically conductive paste.
 7. The displaydevice according to claim 1, wherein the resin substrate and the activematrix substrate are bonded with an adhesive comprising a materialhaving a thermoplastic property.
 8. The display device according toclaim 1, wherein the resin substrate and the active matrix substrate arebonded with an adhesive comprising an anisotropic conductive resin or asilver paste.
 9. The display device according to claim 1, wherein theresin substrate is a film substrate, and is detachably bonded to theactive matrix substrate.
 10. The display device according to claim 9,wherein the film substrate is made of a resin comprising polyimide orepoxy.
 11. The display device according to claim 1, further comprising asemiconductor chip of an external circuit, said semiconductor chip beingmounted on the resin substrate and is connected to the bus line.
 12. Thedisplay device according to claim 11, wherein the semiconductor chip isburied in the via hole.
 13. The display device according to claim 1,wherein the bus line in the multi-layer bus line-equipped section is athick film.
 14. The display device according to claim 13, wherein theinsulator in the multi-layer bus line-equipped section is a thick film.15. A display device comprising: an active matrix substrate having aperipheral portion and a driver circuit section comprising a pluralityof circuit elements and a plurality of polycrystalline silicon thin filmtransistors; a counter substrate; a liquid crystal material filledbetween the active matrix substrate and the counter substrate; and anindividually-wired line array for supplying a clock signal, a datasignal or electric power to the plurality of circuit elements in thedriver circuit section, wherein the individually-wired line array isextended to the peripheral portion of the active matrix substrate,wherein: the active matrix substrate has a recessed groove located inthe peripheral portion; a bus line connected to the individually-wiredline array is buried in the groove, the bus line is a layered structurecomprising a copper foil layer, a copper plating layer, and agold-nickel plating layer.
 16. A display device comprising: an activematrix substrate having a peripheral portion and a driver circuitsection comprising a plurality of circuit elements and a plurality ofpolycrystalline silicon thin film transistors; a counter substrate; aliquid crystal material filled between the active matrix substrate andthe counter substrate; and an individually-wired line array forsupplying a clock signal, a data signal or electric power to theplurality of circuit elements in the driver circuit section, wherein theindividually-wired line array is extended to the peripheral portion ofthe active matrix substrate, wherein: the active matrix substratecomprises an organic resin layer in the peripheral portion thereof, aconnecting electrode, and a bus line connected to the individually-wiredline array and buried in the organic resin layer; the organic resincomprises a photosensitive resin; the organic resin layer has a via holeformed by photolithography; and the bus line is electrically connectedto the individually wired line array via the connecting electrodelocated in the via hole.
 17. The display device according to claim 16,wherein the bus line is an electrically conductive thermosetting resin.18. The display device according to claim 15, wherein the bus line is apre-formed metal fine wire.
 19. The display device according to claim16, wherein the bus line is a pre-formed metal fine wire.
 20. Thedisplay device according to claim 16, wherein the bus line is producedby plating.
 21. The display device according to claim 20, wherein thebus line is a layered structure comprising a copper foil layer, a copperplating layer, and a gold-nickel plating layer.
 22. The display deviceaccording to claim 15, wherein the bus line is formed by depositing inwhich a thin, electrically conductive layer is formed in advance and aplurality of different metal layers are selectively deposited on theelectrically conductive layer.
 23. The display device according to claim16, wherein the bus line is formed by depositing in which a thin,electrically conductive layer is formed in advance and a plurality ofdifferent metal layers are selectively deposited on the electricallyconductive layer.
 24. The display device according to claim 1, wherein,in place of the liquid crystal, a rare gas is located between thesubstrates, the rare gas for forming a plasma discharge to perform adisplay operation.